1. Field of the Invention
The present invention relates generally to electrostatic discharge (ESD) protection for integrated circuits, and more particularly to clamp circuits having p-channel field effect transistors as the primary current carrying elements.
2. Background
As is well known, the build up of static charge may lead to extremely high voltage developed near an integrated circuit (IC). Electrostatic discharge (ESD) refers to the phenomenon of the electrical discharge of high current for short duration resulting from the build up of static charge on a particular IC package, or on a nearby human handling that particular IC package. ESD is a serious problem for semiconductor devices since it has the potential to destroy an entire IC. Since ESD events occur often across the silicon circuits attached to the package terminals, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits. FIG. 1 shows a simple, well-known ESD input protection circuit, wherein a grounded gate NFET has a drain junction breakdown voltage lower than the gate dielectric breakdown voltage.
Ideally, an ESD protection circuit should be able to protect an IC against any conceivable static discharge by non-destructively passing large currents through a low impedance path in a short time.
One difficulty in designing ESD protection circuits is the demanding performance requirements that must be met. For example, one of the primary industry standards for measuring ESD robustness (MIL-STD-883C method 3015.7 Notice 8 (1989), and its follow-on Human Body Model (HBM) standard No. 5.1 (1993) from the EOS/ESD Association) requires ESD zapping for what can be a large number of pin and power supply combinations. In the past ESD protection circuits have had difficulty meeting these stringent requirements while maintaining adequate noise immunity.
ICs have come under pressure in HBM tests because of repeated stressing of the power supply rails, leading to wearout of various breakdown points, such as the Vcc lines. A reliable power supply clamp is needed to reduce the susceptibility of the Vcc bus to failure mechanisms related to ESD testing. ESD protection of input and output pins becomes simpler with a reliable power supply clamp because ESD current can be routed to one supply or another through forward-biased diodes, regardless of polarity.
The physical dimensions of circuit elements in integrated circuits such as microprocessors are becoming smaller with each new generation of semiconductor manufacturing processes. Although these smaller dimensions aid in increasing the operating speed of ICs, an adverse impact of reducing dimensions is the increased sensitivity of circuit elements such as FETs, and more particularly the thin gate insulator layers of FETs, to high electric fields. One technique used to overcome this increased sensitivity is to reduce the operating voltage of an IC. However to maintain compatibility with previous generations of semiconductor products, it has been necessary to provide ICs with interface circuits that are interoperable with older generation ICs that operate at higher voltages. This has resulted in the practice of designing ICs having a core that operates from a first power supply voltage, and Input/Output (I/O) circuitry, typically around the physical periphery of an IC, which operates from a higher power supply voltage.
Diode strings have been used successfully to couple peripheral power supplies to their corresponding core power supplies during ESD events, while affording voltage isolation adequate to prevent unwanted coupling during ordinary operation. In their role as charge couplers, they have enhanced charged device model (CDM) performance. Observations indicate that power supply clamps help ICs with multiple, electrically separated power supplies to pass the multiple pin combination tests of the HBM ESD test, which is the most commonly used test in the industry. Further observations indicate that chips with multiple, electrically separated power supplies that do not incorporate power supply clamps have had difficulty passing the HBM pin combination tests.
Cantilever diode power supply clamps depend on multiple forward diode drops to achieve their functionality. FIGS. 2 and 3 show cantilevered diode power supply clamps and FIG. 4 shows a pulsed I-V curve indicating the performance of the circuits of FIGS. 2 and 3.
In creating low voltage CMOS processes, the FET gate insulator and corresponding insulator and junction breakdown voltages scale downward. Therefore a cantilever diode string of sufficient length to achieve ESD protection functionality would be too long for clamping on-chip power supplies because the number of forward diode drops needed for heavy current conduction (as seen in FIG. 4) does not scale along with other CMOS physical and electrical parameters.
What is needed is power supply clamping and improved coupling of the charge to safe discharge paths.
What is further needed is an area-efficient ESD protection circuit adapted for low voltage Complementary Metal Oxide Semiconductor (CMOS) processes.
What is further needed is an efficient ESD protection device for higher than core voltage power supplies on CMOS processes, where the total supply voltage must be dropped across two gate oxides instead of one for reasons of reliability.